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PCI Express to Serial ATA 2 PORT W-3132E

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Introduction

The Silicon Image SiI3132 is a two-port PCI Express to Serial ATA controller. The SiI3132 is designed to provide multiple port serial ATA connectivity with minimal host overhead and host to device latency. The SiI3132 supports a 1-lane 2.5 Gb/s PCI Express bus and the Serial ATA Generation 2 transfer rate of 3.0 Gb/s (300 MB/s).

System instruction

LINUX, Windows, 95,  98, ME, 2000, XP

Specifications

• Host Protocol
• Optimized for transaction oriented designs – minimal Host overhead
• Supports two command issuance mechanisms
• Efficient in both embedded and PC implementations
• Reduces dependency on bridge behavior
• Designed to leverage PCI-X burst capabilities
• Full 64 bit functionality
• Supports up to 4Mbit external Flash for BIOS expansion
• Supports a master/slave I2C interface
• Supports external Flash or serial EEPROM for programmable subsystem vendor ID / subsystem product ID
• Fabricated in a 0.18＆#65533;＆#65533;nCMOS process with a 1.8 volt core and 3.3 volt I/Os
• Available in an 88-pin QFN package (10x10 mm, 0.4 mm lead pitch). An EPAD must be soldered to PCB GND
• JTAG boundary scan

PCI Express Features

• Supports 1-lane 2.5 Gb/s PCI Express
• Internal application interface multiplexed to 2 ports
• All registers appear in unified memory space
• All registers accessible through I/O space
• Full-chip command completion status accessible with single PCI Express access

Serial ATA Features

• Integrated Serial ATA Link and PHY logic
• Compliant with Serial ATA 1.0 specifications
• Supports Serial ATA Generation 2 transfer rate of 3.0 Gb/s
• Plesiochronous, Single PLL architecture, 1 PLL for 2 ports
• Output Swing Control
• Supports two independent Serial ATA channels
• Independent Link, Transport, and data FIFO
• Independent command fetch, scatter/gather, and command execution
• Hard coded state machines – no code space or download
• Supports Legacy Command Queuing (LCQ)
• Supports Native Command Queuing (NCQ)
• Supports Non-zero offsets NCQ
• Supports Out of order data delivery NCQ
• Supports FIS-based switching with Port Multipliers
• 31 Commands and Scatter/Gather Tables per Port on-chip
• Protocol Override per Command
• Staggered Spin-up Control

References

• Serial ATA / High Speed Serialized AT Attachment specification, Revision 1.0
• PCI Express Base Specification Revision 1.0a